1、The sequence control circuit of DATA collection is designed with finite state machine of VHDL.
用VHDL（甚高速集成電路硬件描述語言）有限狀態(tài)機(jī)設(shè)計了數(shù)據(jù)采集時序的控制電路。

2、I use a finite state machine in the regular expression is achieved.
我的一個利用有限狀態(tài)機(jī)的正則表達(dá)式的實現(xiàn)。

3、You used the finite state machine pattern to design this behavior.
我們使用有限狀態(tài)機(jī)模式設(shè)計了這種行為。

4、An IP package method based on Finite State Machine is proposed.
文中提出了一種基于狀態(tài)機(jī)的IP封裝方法。

5、Studies issues in the finite state machine design in PCI bus interface controllers.
研究有限狀態(tài)機(jī)與PCI總線接口控制器的設(shè)計問題。

6、The finite state machine pattern used to design this behavior makes its logic transparent.
設(shè)計此行為所用的有限狀態(tài)機(jī)模式使邏輯清晰透明。

7、Therefore, the introduction of the finite state machine concepts.
為此，引入有限狀態(tài)機(jī)的概念。

8、Meanwhile, we also made use of the finite state machine inference algorithm.
同時，我們還提出了利用有限狀態(tài)機(jī)進(jìn)行推理的算法。

9、As a digital logic design engineer, a problem of designing a finite state machine is often met.
作為一個數(shù)字邏輯工程師，經(jīng)常會碰到設(shè)計一個有限狀態(tài)機(jī)的問題。

finite state machine翻譯